Computing module with serial data connectivity

ABSTRACT

A computing module includes an interface to asynchronously, serially exchange parallel system bus data with one or more other modules of a computer system that includes the computing module. The computing module can asynchronously, serially transfer first parallel bus data to another module of the computer system, and can asynchronously, serially receive second parallel bus data from another module of the computer system.

RELATED APPLICATIONS

This application is a Continuation of U.S. patent application Ser. No.13/652,823, filed Oct. 16, 2012, which in turn was a Continuation ofU.S. patent application Ser. No. 13/240,773, now U.S. Pat. No.8,291,140, filed Sep. 22, 2011, which in turn was a Continuation of U.S.patent application Ser. No. 12/644,511, now U.S. Pat. No. 8,060,675,filed Dec. 22, 2009, which in turn was a Continuation of U.S. patentapplication Ser. No. 11/300,131, now U.S. Pat. No. 7,657,678, filed Dec.13, 2005, which in turn was a Continuation of U.S. patent applicationSer. No. 09/559,678, now U.S. Pat. No. 7,734,852, filed Apr. 27, 2000.U.S. patent application Ser. No. 09/559,678, now U.S. Pat. No.7,734,852, claims the benefit of U.S. Provisional Application No.60/198,317, filed Apr. 19, 2000. U.S. patent application Ser. No.09/559,678, now U.S. Pat. No. 7,734,852, is a continuation-in-partapplication of U.S. application Ser. No. 09/130,057, filed Aug. 6, 1998,now U.S. Pat. No. 6,088,752. U.S. patent application Ser. No.09/559,678, now U.S. Pat. No. 7,734,852, is also a continuation-in-partapplication of U.S. application Ser. No. 09/130,058 filed Aug. 6, 1998,now U.S. Pat. No. 6,070,214. U.S. patent application Ser. No.09/559,678, now U.S. Pat. No. 7,734,852 is also related to U.S. patentapplication Ser. No. 08/679,131, now U.S. Pat. No. 5,941,965. All suchapplications are hereby incorporated herein by reference in theirentireties.

FIELD OF INVENTION

The present invention is generally related to computers and dataprocessing systems, and more particularly to computer systems having atleast one host processor and connectable to a plurality of peripherals,expansion devices, and/or other computers, including notebook and otherportable and handheld computers, storage devices, displays, USB, IEEE1394, audio, keyboards, mice and so forth.

BACKGROUND

Computer systems today are powerful, but are rendered limited in theirability to be divided into modular components due to a variety oftechnical limitations of today's PCI bus technology. And in theirability to adapt to changing computing environments. The PCI bus ispervasive in the industry, but as a parallel data bus is not easilyextended over any distance or bridged to other remote PCI based devicesdue to loading and physical constraints, most notably the inability toextend the PCI bus more than a few inches. Full bridges are known, suchas used in traditional laptop computer/docking stations. However,separating the laptop computer from the docking station a significantdistance has not been possible. Moreover, the processing power ofcomputer systems has been resident within the traditional computer usedby the user because the microprocessor traditionally is directlyconnected to and resident on the PCI motherboard. Thus, upgradingprocessing power usually meant significant costs and/or replacing thecomputer or computer system.

PCI

The PCI bus is primarily a wide multiplexed address and data bus thatprovides support for everything from a single data word for everyaddress to very long bursts of data words for a single address, with theimplication being that burst data is intended for sequential addresses.Clearly the highest performance of the PCI bus comes from the bursts ofdata, however most PCI devices require reasonable performance for eventhe smallest single data word operations. Many PCI devices utilize onlythe single data mode for their transfers. In addition, starting with theimplementation of the PCI 2.1 version of the specification, there hasbeen at least pseudo isochronous behavior demanded from the bus placinglimits on an individual device's utilization of the bus, thus virtuallyguaranteeing every device gets a dedicated segment of time on a veryregular interval and within a relatively short time period. Thefundamental reason behind such operation of the PCI bus is to enablesuch things as real time audio and video data streams to be mixed withother operations on the bus without introducing major conflicts orinterruption of data output. Imagine spoken words being broken intosmall unconnected pieces and you get the picture. Prior to PCI 2.1 theseartifacts could and did occur because devices could get on the bus andhold it for indefinite periods of time. Before modification of the specfor version 2.1, there really was no way to guarantee performance ofdevices on the bus, or to guarantee time slot intervals when deviceswould get on the bus. Purists may argue that PCI is still theoreticallynot an isochronous bus, but as in most things in PC engineering, it isclose enough.

Traditional High Speed Serial

Typical high speed serial bus operation on the other hand allows thepossibility of all sizes of data transfers across the bus like PCI, butit certainly favors the very long bursts of data unlike PCI. The typicaloperation of a serial bus includes an extensive header of informationfor every data transaction on the bus much like Ethernet, which requireson the order of 68 bytes of header of information for every datatransaction regardless of length. In other words, every data transactionon Ethernet would have to include 68 bytes of data along with the headerinformation just to approach 50% utilization of the bus. As it turns outEthernet also requires some guaranteed dead time between operations to“mostly” prevent collisions from other Ethernet devices on the widelydisperse bus, and that dead time further reduces the averageperformance.

The typical protocol for a serial bus is much the same as Ethernet withoften much longer header information. Virtually all existing serial busprotocol implementations are very general and every block of data comeswith everything needed to completely identify it. FiberChannel (FC) hassuch a robust protocol that virtually all other serial protocols can betransmitted across FC completely embedded within the FC protocol, sortof like including the complete family history along with object size,physical location within the room, room measurements, room number,street address, city, zip code, country, planet, galaxy, universe, . . .etc. and of course all the same information about the destinationlocation as well, even if all you want to do is move the object to theother side of the same room. Small transfers across many of theseprotocols, while possible, are extremely expensive from a bandwidthpoint of view and impractical in bus applications where small transfersare common and would be disproportionally burdened with more highoverhead than actual data transfer. Of course the possibility ofisochronous operation on the more general serial bus is not veryreasonable.

Recreating High Speed Serial for PCI

In creating the proprietary Split-Bridge™ technology, Mobilityelectronics of Phoenix Ariz., the present applicant, actually had to goback to the drawing board and design a far simpler serial protocol toallow a marriage to the PCI bus, because none of the existingimplementations could coexist without substantial loss of performance.For a detailed discussion of Applicant's proprietary Split-Bridge™technology, cross reference is made to Applicant's co-pending commonlyassigned patent applications identified as Ser. Nos. 09/130,057 and09/130,058 both filed Aug. 6, 1998, the teachings of each incorporatedherein by reference. The Split-Bridge™ technology approach isessentially custom fit for PCI and very extensible to all the otherperipheral bus protocols under discussion like PCIx, and LDT™ set forthby AMD Corporation. LDT requires a clock link in addition to its datalinks, and is intended primarily as a motherboard application, whereinSplit-Bridge™ technology is primarily intended to enable remote busrecreation. As the speeds of motherboard buses continue to grow faster,Split-Bridge™ can be readily adapted to support these by increasing theserial bus speed and adding multiple pipes. Split-Bridge™ technologyfundamentals are a natural for extending anything that exists within acomputer. It basically uses a single-byte of overhead for 32 bits ofdata and address—actually less when you consider that byte enables,which are not really “overhead”, are included as well.

Armed with the far simpler protocol, all of the attributes of the PCIbus are preserved and made transparent across a high speed serial linkat much higher effective bandwidth than any existing serial protocol.The net result is the liberation of a widely used general purpose bus,and the new found ability to separate what were previously consideredfundamental inseparable parts of a computer into separate locations.When the most technical reviewers grasp the magnitude of the invention,then the wheels start to turn and the discussions that follow open up anew wealth of opportunities. It now becomes reasonable to explore someof the old fundamentals, like peer-to-peer communication betweencomputers that has been part of the basic PCI specification from thebeginning, but never really feasible because of the physical limits ofthe bus prior to Split-Bridge™ technology. The simplified single-byteoverhead also enables very efficient high speed communication betweentwo computers and could easily be extended beyond PCI.

The proprietary Split-Bridge™ technology is clearly not “just anotherhigh speed link” and distinguishing features that make it differentrepresent novel approaches to solving some long troublesome systemarchitecture issues.

First of all is the splitting of a PCI bridge into two separate anddistinct pieces. Conceptually, a PCI bridge was never intended to beresident in two separate modules or chips and no mechanism existed toallow the sharing of setup information across two separate and distinctdevices. A PCI bridge requires a number of programmable registers thatsupply information to both ports of a typical device. For the purpose ofthe following discussion, the two ports are defined into a north andsouth segment of the complete bridge.

The north segment is typically the configuration port of choice and thesouth side merely takes the information from the registers on the northside and operates accordingly. The problem exists when the north andsouth portions are physically and spatially separated and none of theregister information is available to the south side because all theregisters are in the north chip. A typical system solution conceived bythe applicant prior to the invention of Split-Bridge™ technology wouldhave been to merely create a separate set of registers in the south chipfor configuration of that port. However, merely creating a separate setof registers in the south port would still leave the set up of thoseregisters to the initialization code of the operating system and hencewould have required a change to the system software.

Split-Bridge™ technology, on the other hand, chose to make the physicalsplitting of the bridge into two separate and spaced devices“transparent” to the system software (in other words, no knowledge tothe system software that two devices were in fact behaving as one bridgechip). In order to make the operations transparent, all accesses to theconfiguration space were encoded, serialized, and “echoed” across theserial link to a second set of relevant registers in the south side.Such transparent echo between halves of a PCI bridge or any other busbridge is an innovation that significantly enhances the operation of thetechnology.

Secondly, the actual protocol in the Split-Bridge™ technology is quiteunique and different from the typical state of the art for serial busoperations. Typically transfers are “packetized” into block transfers ofvariable length. The problem as it relates to PCI is that the completelength of a given transfer must be known before a transfer can start sothe proper packet header may be sent.

Earlier attempts to accomplish anything similar to Split-Bridge™technology failed because the PCI bus does not inherently know from onetransaction to the next when, or if, a transfer will end or how long ablock or burst of information will take. In essence the protocol for theparallel PCI bus (and all other parallel, and or real time busses forthat matter) is incompatible with existing protocols for serial buses.

An innovative solution to the problem was to invent a protocol for theserial bus that more or less mimics the protocol on the PCI. With suchan invention it is now possible to substantially improve the performanceand real time operation here to for not possible with any existingserial bus protocol.

The 8 bit to 10 bit encoding of the data on the bus is not new, butfollows existing published works. However, the direct sending of 32 bitsof information along with the 4 bits of control or byte enables, alongwith an additional 4 bits of extension represents a 40 bit for every 36bits of existing PCI data, address, and control or a flat 10% overheadregardless of the transfer size or duration, and this approach is newand revolutionary. Extending the 4 bit extension to 12 or more bits andincluding other functionality such as error correction or retransmitfunctionality is also within the scope of the Split-Bridge™ technology.

New Applications of the Split-Bridge™ Technology

Basic Split-Bridge™ technology was created for the purpose of allowing alow cost, high speed serial data communications between a parallelsystem bus and remote devices. By taking advantage of the standard andpervasive nature of the PCI bus in many other applications in computing,dramatic improvements in the price performance for other machines isrealized. The present invention comprises a revolutionary applicationrendered possible due to the attributes of applicant's proprietarySplit-Bridge™ technology.

SUMMARY

The present invention achieves technical advantages as a modularcomputer system having a universal connectivity station adapted toconnect and route data via serial data links to a plurality of devices,these serial links and interfaces at each end thereof employingproprietary Split-Bridge™ technology disclosed and claimed in co-pendingand commonly assigned patent applications identified as Ser. Nos.09/130,057 and 09/130,058, the teachings of which are incorporatedherein by reference.

The present invention derives technical advantages as a modular computersystem by separating into two or more spatially separate and distinctpieces, a computer core and a universal connectivity station (UCS). Thecore is the performance module of the modular computer system and mayinclude some or all of the central processing unit (CPU), memory, AGPGraphics, and System Bus Chip adapted to communicably couple these threetogether or in combination with other items. The UCS communicablycouples the processor module via high speed serial links based on theproprietary Split-Bridge™ technology of Mobility Electronics of PhoenixAriz., the applicant of the present invention, to other computers or toother individual modules such as storage modules including hard diskdrives, a user interface module consisting of a keyboard, mouse, monitorand printer, as well as a LAN Module such as any Internet connection oranother UCS, another UCS, audiovisual device, LAN storage just to name afew. In addition, the UCS is adapted to couple via a Split-Bridge™technology serial link with a portable or handheld computer or deviceremotely located from the UCS but still functionally coupled to themodular computer system via the UCS. The UCS and associatedSplit-Bridge™ technology serial links are all transparent to the moduleswhich can have parallel data busses including those based on PCI orCardbus architectures.

The modular computer system of the present invention including the UCSis a novel approach to computer architecture and upgrade ability.Advantageously, the separate performance module may be selectivelyupgraded or modified as desired and as technology increases theperformance of key components including microprocessor speed, standards,and architectures without necessitating the replacement or modificationof the rest of the computer system. The UCS allows the performancemodule to be upgraded while the rest of the system devices coupledthereto do not need to be modified. Upgrading to single or multipleprocessors in the performance module or modules is readily possible.Whole organizations can standardize to a single UCS regardless of thetype of performance or portability required by the users, thusaddressing for the first time the means of systems level support. Insecurity sensitivity environments, it is possible to separate the“stored media” or computer central processor, or any other component ofthe system and connectivity from the operators, and still maintain thespeed element so important in today's businesses.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates prior art computer systems depicted as a traditionalperformance desk top computer shown at 10, and a portable computingdevice 12, such as a notebook or laptop computer, mechanically coupledto mechanical docking station 14;

FIG. 2 is a block diagram of a prior art bridge 16 used to couple twosystem computing buses, such as used between the portable computingdevice 12 and the mechanical docking station 14 shown in FIG. 1;

FIG. 3 illustrates the proprietary Split-Bridge™ technology serialcommunication technology of the applicant enabling high speed serialcommunications within the modular computer system of the presentinvention; and

FIG. 4 is a block diagram of the modular computer system of the presentinvention utilizing a universal connectivity station (UCS) communicablycoupled to a plurality of devices via serial links, such as theSplit-Bridge™ technology serial links employed using fixed wire,optical, or wireless communication links.

DETAILED DESCRIPTION

Referring to FIG. 3, there is depicted the proprietary Split-Bridge™technology serial communications technology of the present applicant,discussed in great detail in commonly assigned U.S. patent applicationSer. No. 09/130,057 filed Aug. 6, 1998, and Ser. No. 09/130,058 alsofiled Aug. 6, 1998 the teachings of which are incorporated herein byreference.

Applicant Split-Bridge™ technology revolutionizes the status quo forcomputer systems. The Split-Bridge™ technology does not require the needfor custom hardware or custom software to achieve full performanceserial communication between devices, including devices having paralleldata buses including the PCI bus. In fact, for each device in a modularcomputer system, the Split-Bridge™ technology appears just like astandard PCI bridge, and all software operating systems and devicedrivers already take such standard devices into consideration. Byutilizing standard buses within each device operating within the modularcomputer system, each device does not require any additional supportfrom the Operating System (OS) software. The modular computing systemhas simple elegance, allowing the PCI bus which is so pervasive in thecomputer industry, that possible applications of the initial PCI form ofSplit-Bridge™ technology are all most limitless.

Originally implemented in PCI, there is nothing fundamental that tiesthe Split-Bridge™ technology to PCI, and thus, the Split-Bridge™technology can migrate as bus architectures grow and migrate. The 64 bitPCI is compatible with the Split-Bridge™ technology, as is future PCIxand/or LDT or other bus technologies that are currently underconsideration in the industry and which are straight forward transitionsof the Split-Bridge™ technology. Implementations with other protocols orother possible and natural evolutions of the Split-Bridge™ technology,including digital video (DV) technology that can be streamed over thehigh-speed serial link.

Referring to FIG. 4, there is depicted at 20 a modular computer systemaccording to one illustrative embodiment of the present invention. Themodular computer system 20 is based around one or more universalconnectivity stations generally shown at 22 each having a plurality ofinterface ports 24 which are preferably based on the proprietarySplit-Bridge™ technology of the present applicant, Mobility Electronicsof Phoenix Ariz. Each UCS 22 provides input/output, or I/O, capabilityof the computer or computer system 20, as well as modular expansioncapability and features. UCS 22 includes all possible variations andcombinations of port replication and connectivity, including but notlimited to the following ports: P/S2, mouse and keyboard, serial,parallel, audio, USB, IEEE 1394, or firewire, SCSI, and the like. EachUCS 22 also includes the ability to expand the capability or features ofthe computer system 20 by adding any type of drive bays, including EIDE,USB, and 1394 CD Roms, DVD's, hard drives, tape back up's, ZIP Drives®,Jazz® drives, and the like.

A plurality of interconnecting and interactive devices are communicablycoupled to each UCS 22 via respective high speed serial links generallyshown at 26 based on the proprietary Split-Bridge™ technology. In thehardwire embodiment, the serial links 26 comprise of a pair of simplexlinks forms a duplex link interconnecting each end of the Split-Bridge™technology interfaces as shown. The serial links 26 may also employoptical fiber and optical transceivers if desired. The various modulesmaking up modular computer system 20 may include, and a plurality of,but are not limited to, a memory/storage device 30, servers 32 havingone or multiple processors and possibly serving other UCS's 22, asshown, and modular computer systems, remote users and so forth, adisplay 34, a portable computing device 36, such as a notebook computer,a laptop computer, a portable digital assistant (FDA), and a remotewireless peripheral 38 which may interconnected via a wireless linkshown at 40 and implementing the proprietary Split-Bridge™ technology.Examples of remote wireless terminals 38 may include 3rd generation (3G)devices now being developed and employed, including wireless personaldevices having capabilities for voice, data, video and other forms ofinformation which can be unidirectionally or bidirectionally streamedbetween the remote peripheral 38 and UCS 22. An appropriate antennaresides at each of the remote peripheral 38 and UCS 22 which areinterconnected to respective transceivers communicably coupled to therespective ends of the Split-Bridge™ technology interfaces.

Moreover, multiple UCS's 22 can be integrated to communicate with eachother via serially links 26, each UCS's 22 locally serving multiplemodules. Multiple computers can be connected to a common UCS, or tomultiple UCS's. For example, a computer or server room can have racks ofcomputer processors or servers, each separately connected over a systemof up to hundreds of feet, to one or many UCS's located throughout anoffice or other environment. This allows the desktop to have just aterminal or whatever capabilities the IT manager desires, enhancingsecurity and control.

System 20 also provides the ability to simultaneously connect multiplecomputers 36 and allows full peer-to-peer communications, allowing theprocessor module (CPU) 42 to communicate with the portable devicecomputer 36 or to the computer room computers 32, allowing all of thesecomputers to share information and processing capability. This alsoallows certain of the computers, such as the portable computer 36, toupgrade its processing capability when it is connected to the UCS 22with other higher capability computers.

Still referring to FIG. 4, the modular computer system 20 of the presentinvention further comprises a processor module 42, which may be remotelypositioned from the UCS 22, but for purposes of inclusion, couldinternally reside with the UCS 22. The processor module 42, from aperformance point of view, is the heart and sole of the modular computersystem 20 and can be made up of one or more core parts including: theCPU, memory, APG Graphics, and a system bus interface to connect theother 3 together. The processor module 42 operates in conjunction withmemory such as a hard disk drive, which can reside within the processormodule 42, or be remotely located as shown at 30 if desired. The APGGraphics could be located separately within the system andinterconnected via a serial link 26, or even located within UCS 22 ifdesired.

Advantageously, the processor module 42 which may comprise of a highspeed microprocessor or microprocessors, digital signal processors(DSP's), and can be upgraded or interchanged from the systems 20 withouteffecting the other devices or operation of the system, therebypermitting increased performance at a very low cost. Computers todaytypically require the replacement or upgrading of other devices when theperformance portion of the computer system is replaced. The modularcomputer system 20 of the present invention revolutionizes the computerarchitectures available by separating out the processor module 42 fromthe rest of the computer system 20. Each of the modules 30,32,34,36, and38 all have functional access and use of the processor module 42 via theUCS 22 over the respective serial links 26 and 40, and from aperformance point of view, appear to each of these devices to behardwired to the processor module 42. That is, the Split-Bridge™technology links interconnecting each of the devices via the UCS 22 tothe processor module 42 is transparent to each device, thus requiring nochange to the OS of each device, the format of data transfertherebetween, or any other changes. This is rendered possible by therevolutionary Split-Bridge™ technology.

Another advantage of computer system 20 is that the data module 30 maybe customized, portable, and used only by one user. This allows the userto take the portable module 30 with them from location to location,system 20 to system 20. The data module 30 can store each user's uniqueinformation, and can be accessed and used on any processor module 42 andUCS 22.

As discussed in considerable detail in the cross-referenced and commonlyassigned patent applications, the Split-Bridge™ technology provides thatinformation from the parallel buses of each device be first loaded intofirst-in first-out (FIFO) registers before being serialized into framesfor transmission over the high speed serial link. Received frames aredeserialized and loaded into FIFO registers at the other end thereof,such as UCS 22, for being placed onto the destination bus of theopposing device. Interrupts, error signals and status signals are sentalong the serial link. Briefly, the proprietary Split-Bridge™ technologytakes address and data from a bus, one transaction at a time, togetherwith 4 bits that act either as control or byte enable signals. Two ormore additional bits may be added to tag each transaction as either anaddressing cycle, an acknowledging of a non-posted write, a data burst,end of data burst or cycle. If these transactions are posted writes theycan be rapidly stored in a FIFO register before being encoded into anumber of frames that are sent serially over the link. When pre-fetchedreads are allowed, the FIFO register can store pre-fetched data in casethe initiator requests it. For single cycle writes or other transactionsthat must await a response, the bridge can immediately signal theinitiator to retry the request, even before the request is passed to thetarget.

In the preferred embodiment of the modular computer system of thepresent invention, one or more of the busses in the plurality ofdevices, as well as in the UCS 22, employ the PCI or PCMCIA standard,although it is contemplated that other bus standards can be used aswell. The preferred Split-Bridges™ technology operates with a pluralityof configuration registers that is loaded with information specifiedunder the PCI standard. The Split-Bridges™ technology transfersinformation between busses depending on whether the pending addressfalls within a range embraced by the configuration registers. Thisscheme works with devices on the other side of the Split-Bridge™technology, which can be given unique base addresses to avoid addressingconflicts.

As disclosed in great detail in the co-pending and cross-referencedcommonly assigned patent applications, the Split-Bridges™ technology maybe formed as two separate application-specific integrated circuits(ASICs) joined by a duplex link formed as a pair of simplex links.Preferably, these two integrated ASICs have the same structure, but canact in two different modes in response to a control signal applied toone of its pins. Working with hierarchical busses (primary and secondarybusses) these integrated circuits are placed in a mode appropriate forits associated bus. The ASIC associated with the secondary buspreferably has an arbitrator that can grant masters control of thesecondary bus. The ASIC can also supply a number of ports to supportother devices such as a USB and generic configurable I/O ports, as wellas parallel and serial ports.

The UCS preferably comprises a PCI bus having a plurality of PC cardslots located with the UCS housing. Each PC card slot is provided with aSplit-Bridge™ technology interface, and preferably one of the ASICsassembled with a standardized serial connector comprising at least 4pins, as depicted in the cross referenced commonly assigned patentapplications, the teachings of which are incorporated herein byreference.

The modular computer system 20 of the present invention derivestechnical advantages in that the UCS station 22 with its associatedinterface cards and parallel data bus interconnecting each interfacecard, is truly functionally transparent to each of the interconnectedmodules including the memory storage device 30, the server 32, thedisplay 34, the portable computing device 36, the remote wirelessperipheral 38, and the processor module 42. This integration of devicesinto a modular computer system has truly enormous potential and usesdepending on the desired needs and requirements of one's computingsystem. However, the physical location and proximity of each of thedevices forming the modular computer system are no longer strictlylimited due to the high speed serial interconnection links of theproprietary Split-Bridge™ technology. Each of the devices can beremotely located, or located in proximity to one another as desired. Forinstance, the display 34 and portable computing device 36 may beresident within one's office, with the UCS 22 in another room, and withthe memory storage device 30, server 32, and performance module 42remotely located in yet still another room or location. Moreover, aplurality of portable computing devices 36 can all be remotely locatedfrom UCS 22, and from each other, allowing networking to modular system20 either through wireless serial links as depicted at 26, or wirelesslyas depicted at 40.

The proprietary Split-Bridge™ technology presently allows for extendedcommunication distances of 5 meters, but through advancement intechnology can continue to be extended. For instance, using opticalcommunication links in place of copper wire simplex links, along withsuitable optical transceivers, can yield links that are exceptionallylong. Using wireless technology, as depicted at 40, allows a remoteperipheral 38 to be located perhaps anywhere in the world, such as byimplementing repeaters incorporating the proprietary Split-Bridge™technology high speed serial communication technology. Additionaltechniques can be used by slowing the transfer rate, and increasing thenumber of pipes, to achieve link distances of hundreds of feet, andallowing the use of CAT5 cable.

Though the invention has been described with respect to a specificpreferred embodiment, many variations and modifications will becomeapparent to those skilled in the art upon reading the presentapplication. It is therefore the intention that the appended claims beinterpreted as broadly as possible in view of the prior art to includeall such variations and modifications.

What is claimed is:
 1. A system, comprising: a module operable toreceive first serial data transmitted over a serial link and to transmitsecond serial data to the serial link, wherein the module includes: areceiver operable to receive the first serial data from the serial link;a first circuit configured to deserialize the first serial data togenerate deserialized data; a decoder configured to decode thedeserialized data; a first buffer operable to store data that has beendeserialized and decoded by the first circuit and the decoder,respectively; a second buffer operable to receive data, wherein thesecond buffer is in data communication with a second circuit that isconfigured to serialize data received via the second buffer to generatethe second serial data; a transmitter operable to transmit the secondserial data to the serial link through the connector; wherein the moduleis configured to determine whether an amount of data stored in the firstbuffer equals or exceeds a fill amount associated with a storagecapacity of the first buffer; and wherein the module is operable togenerate a flow control signal in response to the amount of data storedin the first buffer equaling or exceeding the fill amount, and whereinthe module is further configured to transmit the flow control signalthrough the serial link and the connector without passing the flowcontrol signal through the second buffer.